Memory system



NOV. 24, 1959 K, GANZHORN ET AL 2,914,754

MEMORY SYSTEM 2 Sheets-Sheet 1 Filed Feb. 26, 1957 Nov. 24, 1959 K.GANzHoRN I-:T AI. 2,914,754

MEMORY SYSTEM Filed Feb. 26, 1957 2 Sheets-Sheet 2 R IN" P i I FIG. 2 I

IIC Ro i II Q R l 0 I R-QH-W I-' HR I-a- Hw-I READING R NRIIINGDIRECTION INREcIIoN Iw coIuNN L I --"I f/ 2 F s I izos-RASIC cYcLE I wRow 2\ 0 f `r 1 l IIIIF'IIIRTE y l. l

. 115 RIILsELENcIR 2 r I l LZUS 4*LNRITE DELAY IN VEN TORS KARL GANZHORNTHEODOR EINSELE HANS BOR AUSER FIG.3

"..llifed States.' arent MEMORY SYSTEM Karl Ganzhorn and TheodorEinsele, Sindelfingen, and Hans Bornhauser, Boblingen, Germany,assignors to International Business Machines Corporation, New York,N.Y., a corporation of New York Application February 26, 1957, SerialNo. 542,488 claims priority, application Germany March 17, 1956 11Claims. (Cl. S40- 174) l i column address selection means beingdetermined by the size of thevword and the quantity of words to bestored. Within the linear matrix system itself certaln problems andlimitations are generally recognized.

Therefore, the principal object of 'this invention is to provide animproved linear core matrix storage system that reduces driverrequirements and simplifies address selection.

Another object of this invention is to provide a magnetic core matrixsystem wherein the read pulses of a certain column simultaneouslyserveas half write pulses for the preceding column. l

` Another object is to provide magnetic core matrix system whereinstorage or writing is accomplished by column and row pulses and readingis accomplished only by colu-mn pulses. i Y

Still another object is to provide a magnetic core matrix system whereinreading and writing are in true or com-l plementary form. i

Other objects of the invention will be pointed out in the followingdescription and claims and illustrated in the accompanying drawings,which disclose, by way of examples, the principle of the invention andthe best mode, which has been contemplated, of applying that principle.v

In the drawings:

Fig 1 illustrates a linear magnetic core matrix system in accordancewith the invention.

Fig. 2 is a hysteresis loop illustrating the character of magnetizationof the storage cores.

Fig. 3 illustrates the relative pulse situation in a hypotheticalreading operation.

As illustrated in Fig. l, the cores are arranged in a two-dimensionalmatrix system of nine column-s and ten rows. Such an arrangement permitsthe storage of a word having a length of nine decimal digits or eightdigits and a sign. It is clear that the length of the word may beincreased by simply adding columns of magnetic cores.

Each core 11 has a plurality of conductors therethrough. Shown in thehorizontal direction are conductors 12, 13 and 14, and in the verticaldirection is conductor 16. The premagnetization conductor 12 passes in azigzag fashion through all the rows. Conductor 16, which is energized bydriver 21, is shown as a winding of a few turns in order that a pulse ofsufficient magnitude might be formed during a readout operation.

EQ@ irimanga Nov. 24, 1959 'Line 12 is shown terminating at outputterminal 26,

which may be connected to another core matrix or simply grounded. Theoutput voltage is taken from the true conductor 13 and the complementaryconductor 14, both of which also lperform Va writing function. Thelatter conductors 13 and 14 could also take the form of a winding havinga few turns, if it is desired to develop a higher output voltage and alower half write current.

The single premagnetization conductor 12 is energized by a D.C.potential provided by any conventional source 17. The energization ofparallel-connected conductors 13 (for true storage) and 14 (forcomplement storage) is controlled by conventional gates 18 and 19, whichmay take the form of a manual switch or electronic circuitry. Conductors13 pass through the row ,cores representing the true value of all orderdigits, whereas conductors 14 pass through row cores representing thetens complement value of the digits in each order. Whether a value is tobe written and read as true or complementary depends on which gate 18 or19 is On or operating at the time. Storage gate 20, which also may takeany conventional form, permits the energization of conductor 16,which'is associated with a different column of the matrix. i

Storage driver 21 may take the form of a chain of blocking oscillatorscapable of developing voltage pulses of negative Ipolarity andcalibrated amplitude. Tliese pulses are produced in serial fashionbeginning with column l. Actually ten such pulses are required for eachreadout cycle, since the tenth pulse serves as a half write pulse for`column 9. The requiredV magnitude of the read pulses is obtained by awinding of two turns. The same conductor which forms the windings forreadout afterwards passes in thepopposite direction through thepreceding column of cores with one turn thus forming simultaneously thehalf-write pulse. The negative pulse developed by storage driver 21 iscoupled by a diode 22 and a resistor 23 to all the core windings of thatparticular column. The half write current is capable of rbeing placed atthedesired value by the calibrated voltage amplitude of the blockingoscillators and the resistors 23.

At the right of Fig. l are ten input/ output terminals, each connectedto two diodes 24 and 25. Diode 24 permits 4writing and reading the truenumber, whereas diode 25- controls writing and reading the tenscomplement `of a number. Diode 24 of each input order is associated`with all 4the cores in the row corresponding to that input order. Onthe other hand, diode 25 vof each input order is associated with thecore of column l in the row corresponding to the tens complement andwith the cores of columns 2 to 9 corresponding to the nines complementof the particular input order.

In the case of true storage, diode 24 of the 3 input position, forexample, is associated with the third row of cores', and brings aboutthe storage of a digit 3 in any column selected by storage driver 21,provided that true gate 18 is On at the time. For complementary"storage, diode 25 of row 3 is associated with the rowl"6 coresof'columns "2. to 9and the row 7 core of column 1. Therefore, a digit 7is stored in column l or a digit "6 in any other column selected bystorage driver 21 provided that gate 19 is On at the time.

The magnetization conditions for the disclosed core arrangement aresomewhat different from the common coincidence matrix arrays. Thisresults from the fact that coincidence selection of the cores must beprovided only for writing. Since no row selection is required forreading there are no half read pulses in the disclosed arrangement. Thecores are premagnetized with a constant 4field-Ho (Fig. 2) in thedirection of reading. With conditions for the half'write pulses Withoutpremagnetization, when point P is reached by applying two half writepulses, one half Write pulse brings the magnetization point Q, very nearthe edge of the hysteresis loop. However, with pre-magnetization thepoint Q of one' half write pulse lies to the left of Q1 wherev thechange of magnetization is not so serious as at point Q1.

For reading out of storage, pulse HR is delivered through the selectedcolumn conductor 16 Without the requirement of any other coincidencepulse. This mea-ns that the amplitude of HR can be high, therebyresulting in an increased amplitude of the output pulses. The use ofVhigh reading pulse amplitudes and premagnetization increases the outputvoltage and decreases the switching time, thereby permitting the use offerrite cores with low coercive force.

Fig. 3 illustrates the time relationship between the half-write currentand the reading current for a hypothetical situation in which apreviously stored number 2,100 isto be read out. TheV number is storedin the rst four columns, as shown in Fig. 3. The voltage pulsesdeveloped by storage driver 21 are shown in the top group, and the halfwrite pulses are shown in the bottom group in Fig. 3. The negativereadout pulses are shown in dotted lines in the bottom portion of Fig;3. Although Fig. 3 illustrates half-write pulses4 each for a specifictrue digit representing core in the preceding col-Y umn, actuallyhalf-.write pulses are provided for all the cores in the precedingcolumn. However, since We are assumingl a rewrite. operation, only thesepulses are ofV interest. The half-writecurrent pulse is shown to be halfthe read current pulse IR. With regard to the columnar pulses of Fig. 3,it has been assumed that a group of conventional blocking oscillatorsform driverV 2l. In such a case the trailing edge ofA the pulse`developed by the rst blocking oscillator fires thel second blocking`oscillator, and so on. lt is under-L stood that the premagnetizationinput 1'7, true gate 18 and. storageV gate 20are On atthi-s time.

During the iirst basic cycle of, for example, 2 0 as,

the. pulse developed by driver 2l reads out the lowest.V

order digit from the first column. The second' pulse of driver 21 readsout another 0 from the second column` and simultaneously producesY ahalfwrite pulse in the first column. column, lasting about 2-3 us, isfinished, writing` a new, value or rewriting the old value in the rstcolumn may be accomplished. It is noted that' the readout pulsedeveloped by storage driver 21 is negative in character,

and therefore capable of read out on the true and complementary linesthrough respectivek diodes 24 and 25 during the. time interval thatpositive writing pulses are not available at the input of diodes 24 and25. AThe When the readout from the second,

aiected. The time available for writing is about l5 lts, which issuicient to switch over the cores with a low coercive force and longswitching time.

Returning to our hypothetical reading situation represented by Fig. 3,the third pulse from driver 21 reads out l from the third column andproduces a half write pulse for the second column. The next pulse readsout a 2 from the fourth column and provides a half write i pulse for thepreceding column. The iifth pulse (not shown) does not read out anyvalue, but rsimply serves to provide a half write pulse for the fourthcolumn.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to a preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in theart,without departing from the spirit of the invention.

It is the intention, therefore, to be limited only as indicated by thescope ofthe following claims.

What is claimed is:

l. AV memory system comprising a plurality of magnetic cores arranged incolumns and rows, in which each magnetic core is formed of the materialhaving a substantially rectangular hysteresis curve characteristic,input means for entering data representing pulses into row corescorresponding to the true and complementary form of said datarepresenting pulses, means connected to said input means for determiningwhether whether data storage is to be in true or complementary form, anddriving means for controlling the columns .in which said true and`complementary data are stored.

2. A memory system comprising a plurality of magnetic coresV arranged incolumns and rows, in which each magnetic core is formed of the materialhaving a substantially rectangular hysteresis curve characteristic,input means for entering data representing pulses into -row corescorresponding to the true and complementary form of said datarepresenting pulses, means connected to said input means for determiningwhether data storage is to be in true or complementary form, and drivingmeans for controlling the columns in which said rue and complementarydata are stored with said columnar driving means cooperating with saidinput means for entering data into desired locations of said memorysystem and with said columnar driving means alone serving to readout thetrue or complementary data previously entered into ysaid memory system.

3. A storage unit comprising a plurality of magnetic cores arranged incolumns and rows, in which each magneticl core is formed of the materialhaving a substantially rectangular hysteresis curve characteristic, acore in each column being provided for storing a certain value,

readout negative pulse is necessarily of short duration.

half-write current pulse aloneis incapable of changing pulse are capableof achieving this result.` Itis recog-vv 70 the st ate of the core butthis pulse plus the input row.7

nized'that'the samerow current flows through allthe row cores, but thatonly the row core of the rst Column is.

aiirst winding for entering a true value intoeach row of cores, a secondwinding for entering the complement value into row cores forming thetens complement of the value entered through said iirst winding, inputmeans for energizing said iirst and second windings simultaneously withvalue representing electric pulses, a third Winding forjreading andwriting the true and complementary values in each column, and means forsequentially energizing each of said third windings during thereadingand writing operations, with said third winding in any columnserving to provide a half write pulse 'for all the cores in thepreceding column during a reading operation.

4. A storage unit comprising a plurality of magnetic cores arranged incolumns and rows, in which each mag netic core is formed ofV thematerial having a substantially rectangular hysteresis curvecharacteristic, a core in each column being provided for storing acertain value, a iirstl winding for' each column of cores, means forenergizing each of said first windings sequentially proceeding from thelowest column to the highest column, a second winding connected throughall the column and row windings for pre-magnetizng said cores, means forenergizing said second winding with a constant current of apredetermined magnitude, a third winding for entering a ktrue value intoeach row of cores, a fourth Winding for i entering the complement valueinto row cores from the tens ,complement of the value entered throughsaid third y winding, input pulse means connected to pairs of said thirdVand fourth windings for writing simultaneously with true and complementvalue of the input number, and means connected to all said third andfourth windings for controlling true and complementary reading and fwriting in said storage unit.

5. Akv storage system having ak plurality of magnetic cores arranged incolumns and rows, in which each magnetic core is formed of the materialhaving a substantially rectangular hysteresis curve characteristic, acore` in each column being provided for storing a' certain value,

a iirst winding for storing and reading values in columns,

means for sequentiallyenergizing each of said first windings startingfrom the lowestr'column Yand proceeding to the highest column, a secondwindingfor entering a i true value into each -row of columns, a thirdwinding for entering the complement value into'the row cores, inputmeans for energizing said irst and second wind-v ings simultaneously,and independently operatingr means y connected to said rrst and secondwindings for controlling storage in vtrue and complementary form.

' 6.`AA' storage system havingra plurality of magnetic cores arranged incolumns and rows, in which each magwinding'associated with all of thecores in each row for entering the true value intothe storage system, athird vwinding associated with the row cores forming the tens ncomplement of the value entered through said second 4 winding forentering the complement value kinto said storage system, and input meansfor energizing said rst and second windings simultaneously with saidsecond or third `winding and said first winding cooperating to enterinformation into said storage system and said r'st winding aloneaccomplishing readout from said storage system.

7. A storage system having a plurality of magnetic cores arranged incolumns and rows, in which each magnetic core is formed of the materialhaving a substantially rectangular hysteresis curve characteristic, acore in each column being provided for storing acertain value,comprising a iirst winding for storing and reading out valuessequentially in all columns, means for sequentially energizing each ofsaid first windings starting from the lowest column and proceeding tothe highest column, a second winding for entering atrue value intov eachrow of cores, a third winding for entering the complement value into rowcores forming the tens complement of the value entered through saidfirst winding, and input means for energizing said rst and secondwindings simultaneously.

8. The invention according to claim 7 wherein a single gating means isassociated with a kplurality of irst windings for` resetting saidstorage system.

9. The invention according to claim 7 wherein pairsk of said first andsecond windings are connected to a different input means throughparallel connected diodes.

l0. The invention according to claim 7 wherein said v"iirst winding ineach column is connected through va parallel connected diode resistancearrangement to the output of said drivingmeans.

`l1. The invention according to claim 7, characterized References Citedin the le of this patent vPublication'I: Thesis on Magnetic Cores, by K.Haynes, Dec. 28, 1950, pages 21 to 28, 36 to 45.

